How Big Is A Register Arm
The corporeality of registers depends on the ARM version. According to the ARM Reference Manual, there are xxx general-purpose 32-bit registers, with the exception of ARMv6-M and ARMv7-M based processors. The start xvi registers are accessible in user-level fashion, the additional registers are available in privileged software execution (with the exception of ARMv6-M and ARMv7-M). In this tutorial series nosotros volition work with the registers that are attainable in any privilege mode: r0-15. These sixteen registers tin be separate into two groups: general purpose and special purpose registers.
The following tabular array is merely a quick glimpse into how the ARM registers could chronicle to those in Intel processors.
R0-R12: can exist used during mutual operations to store temporary values, pointers (locations to retentivity), etc. R0, for example, can be referred every bit accumulator during the arithmetic operations or for storing the outcome of a previously chosen function. R7 becomes useful while working with syscalls as it stores the syscall number and R11 helps us to keep track of boundaries on the stack serving as the frame pointer (will be covered later on). Moreover, the part calling convention on ARM specifies that the first 4 arguments of a function are stored in the registers r0-r3.
R13: SP (Stack Pointer). The Stack Pointer points to the pinnacle of the stack. The stack is an area of retention used for function-specific storage, which is reclaimed when the function returns. The stack pointer is therefore used for allocating infinite on the stack, by subtracting the value (in bytes) we desire to allocate from the stack pointer. In other words, if we want to allocate a 32 bit value, we subtract four from the stack arrow.
R14: LR (Link Register). When a function call is made, the Link Register gets updated with a retention address referencing the side by side educational activity where the office was initiated from. Doing this allows the program return to the "parent" function that initiated the "child" function call after the "child" function is finished.
R15: PC (Plan Counter). The Program Counter is automatically incremented by the size of the instruction executed. This size is always four bytes in ARM state and 2 bytes in THUMB mode. When a branch pedagogy is being executed, the PC holds the destination address. During execution, PC stores the address of the electric current teaching plus 8 (2 ARM instructions) in ARM country, and the current teaching plus 4 (two Thumb instructions) in Thumb(v1) country. This is different from x86 where PC always points to the side by side instruction to be executed.
Let's look at how PC behaves in a debugger. We use the following program to store the address of pc into r0 and include ii random instructions. Let's encounter what happens.
.section .text .global _start _start: mov r0, pc mov r1, #two add r2, r1, r1 bkpt
In GDB we set a breakpoint at _start and run information technology:
global environment facility> br _start Breakpoint ane at 0x8054 gef> run
Here is a screenshot of the output we see showtime:
$r0 0x00000000 $r1 0x00000000 $r2 0x00000000 $r3 0x00000000 $r4 0x00000000 $r5 0x00000000 $r6 0x00000000 $r7 0x00000000 $r8 0x00000000 $r9 0x00000000 $r10 0x00000000 $r11 0x00000000 $r12 0x00000000 $sp 0xbefff7e0 $lr 0x00000000 $pc 0x00008054 $cpsr 0x00000010 0x8054 <_start> mov r0, pc <- $pc 0x8058 <_start+iv> mov r0, #2 0x805c <_start+viii> add r1, r0, r0 0x8060 <_start+12> bkpt 0x0000 0x8064 andeq r1, r0, r1, asr #x 0x8068 cmnvs r5, r0, lsl #two 0x806c tsteq r0, r2, ror #18 0x8070 andeq r0, r0, r11 0x8074 tsteq r8, r6, lsl #6
We tin run into that PC holds the address (0x8054) of the adjacent instruction (mov r0, pc) that will be executed. At present let's execute the next pedagogy after which R0 should concord the address of PC (0x8054), correct?
$r0 0x0000805c $r1 0x00000000 $r2 0x00000000 $r3 0x00000000 $r4 0x00000000 $r5 0x00000000 $r6 0x00000000 $r7 0x00000000 $r8 0x00000000 $r9 0x00000000 $r10 0x00000000 $r11 0x00000000 $r12 0x00000000 $sp 0xbefff7e0 $lr 0x00000000 $pc 0x00008058 $cpsr 0x00000010 0x8058 <_start+4> mov r0, #2 <- $pc 0x805c <_start+8> add r1, r0, r0 0x8060 <_start+12> bkpt 0x0000 0x8064 andeq r1, r0, r1, asr #10 0x8068 cmnvs r5, r0, lsl #2 0x806c tsteq r0, r2, ror #18 0x8070 andeq r0, r0, r11 0x8074 tsteq r8, r6, lsl #6 0x8078 adfcssp f0, f0, #four.0
…right? Wrong. Look at the accost in R0. While we expected R0 to contain the previously read PC value (0x8054) information technology instead holds the value which is two instructions ahead of the PC we previously read (0x805c). From this example you tin see that when we directly read PC it follows the definition that PC points to the next instruction; but when debugging, PC points two instructions alee of the electric current PC value (0x8054 + eight = 0x805C). This is because older ARM processors ever fetched two instructions ahead of the currently executed instructions. The reason ARM retains this definition is to ensure compatibility with earlier processors.
Source: https://azeria-labs.com/arm-data-types-and-registers-part-2/
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