Which Instruction Will Set Bits 5 And 2 In Register A?

DATA processing instructions :
We use data processing instructions to dispense data within the registers.

Types for data processing instructions –

Arithmetic instructions
Logical instructions
Multiply instructions
Comparing instructions
Move instructions

Most of the data processing instructions use a barrel shifter to pre-procedure the data of one of their operands. Each operation updates different flags in the cpsr (To learn more about 'CPSR' search "CPSR in ARM").

Let us discuss the instructions in particular.

1. Arithmetic instructions :
The arithmetic instructions mainly implement addition and subtraction of 32bit signed and unsigned values.

Syntax: <educational activity>{<cond>}{s} Rd, Rn, N

ADC	add with 32-bit values and comport	Rd=Rn+N+acquit
Add	add ii 32-scrap values	Rd=Rn+North
RSB	reverse subtract of two 32-bit values	Rd=N-Rn
RSC	reverse subtract with carry of ii 32-bit values	Rd=N-Rn-!(Bear flag)
SBC	subtract with deport of two 32-bit values	Rd=Rn-N-!(Comport flag)
SUB	subtract 2 322-bit values	Rd=Rn-N

N is the outcome of the shift functioning.

Examples –
one. This simple subtract instruction subtracts a value stored in register r2 from a value stored in register r1. The result is stored in register r0

PRE
r0 = 0x00000000 ; As this register is a register to hold the output, that's why information technology is empty before execution
r1 = 0x000000002 ; register r1 holds the value 'two'
r2 = 0x000000001 ; r2 holds another value '1'
SUB r0, r1, r2 ; r0=r1 – r2. Here the subtracted value (r0 – r1) is moved to r0 after performing operation.

POST
r0 = 0x00000001 ; This is the output of above instruction moved to r0 register

2. This opposite subtract education (RSB) subtracts r1 from the constant value #0, writing the result to r0.
Reverse subtraction is helpful for integer values and then that the instruction tin exist subtracted with no complexity.

PRE
r0 = 0x00000000 ; Output register
r1= 0x00000077 ; value to exist contrary subtracted
RSB r0, r1, #0 ; Rd = 0x- – r1

POST
r0 = -r1 = 0xffffff89 ; reversed output gets generated and stored in the register r0

Usage of barrel shifter with arithmetic instructions –
Barrel shifting is one of the powerful features of the ARM teaching fix.
It pre processes one of the operand/ registers before performing operation on it.

Example –

PRE
r0 = 0x00000000
r1 = 0x00000005
ADD r0, r1, r1, LSL #1

Postal service
r0 = 0x0000000f
r1 = 0x00000005

ii. Logical Education –
Logical instructions perform bitwise logical operations on the two source registers.
Syntax: <education>{<cond>} {S} Rd, Rn, N

AND	logical bitwise AND of two 32-scrap values	Rd = Rn & N
ORR	logical bitwise OR of two 32-bit values	Rd = Rn \| N
EOR	logical exclusive OR of two 32-bit values	Rd = Rn ^ Northward
BIC	logical bit clear (AND Non)	Rd = Rn &~ Northward

Example –
ane. This example shows a logical OR operation between registers r1 and r2, r0 holds the result.

PRE
r0 = 0x00000000
r1 = 0x02040608
r2 = 0x10305070
ORR r0, r1, r2

POST
r0 = 0x12345678

two. This case shows a more complicated logical education chosen BIC, which carries out a logical bit clear.

PRE
r1 = 0b1111
r2 = 0b0101
BIC r0, r1, r2

POST
r0 = 0b1010

3. Multiply Instruction –
The multiply instructions multiply the contents of a pair of registers depending upon the instruction, and accumulate the result along with another register . The long multiplies accrue onto a pair of registers representing a 64-bit value. The final result is placed on a destination annals or pair of registers.

Syntax – MLA{<cond>}{S} Rd, Rm, Rs, Rn
MUL{<cond>}{S} Rd, Rm, Rs

MLA	Multiply and accumulate	Rd = (Rm * Rs) + Rn
MUL	multiply	Rd = Rm * Rs

Syntax – <instruction>{<cond>}{S} RdLo, RdHi, Rm, Rs

SMLAL	signed multiply accumulate long	[RdHi, RdLo] = [RdHi, RdLo] + (Rm * Rs)
SMULL	signed multiply long	[RdHi, RdLo] = Rm * Rs
UMLAL	unsigned multiply accumulate long	[RdHi, RdLo] = [RdHi, RdLo] + (Rm * Rs)
UMULL	unsigned multiply long	[RdHi, RdLo] = Rm * Rs

Processor implementation handles the number of cycles taken to execute a multiply instruction.

Example 1 –

This example represents the elementary multiply instruction that multiplies registers r1 and r2 together and places the result into a register r0.
Annals r1 is equal to the value 2, and r2 is equal to 2, then replaced to r0.

PRE
r0 = 0x00000000 ; register to hold the output
r1 = 0x00000002 ; register property the operand i value
r2 = 0x00000002 ; register holding the operand 2 value
MUL r0, r1, r2 ; r0 = r1 * r2

POST
r0 = 0x00000004 ; output of the multiplication operation
r1 = 0x00000002
r2 = 0x00000002 ; operands

Example 2 –

PRE
r0 = 0x00000000
r1 = 0x00000000
r2 = 0xf0000002
r3 = 0x00000002
UMULL r0, r1, r2, r3 ; [r1, r0] = r2 * r3

POST
r0 = 0xe0000004 ; = RdLo
r1 = 0x00000001 ; = RdHi

4. Comparing Instructions –
These instructions are used to compare or examination a register with a 32-chip value. They update the cpsr flag bits according to the result, only practice not touch other registers. Later the bits have been set up, the data can and then be used to change program menstruation past using conditional execution.

Syntax – <instruction>{<cond>} Rn, N

CMN	compare negated	flags set equally a upshot of Rn + N
CMP	compare	flags set equally a result of Rn – North
TEQ	examination for quality of two 32 – bit values	flags set equally a result of Rn ^ Due north
TST	test bits of a 32-chip value	flags fix as a upshot of Rn & North

N is the result of the shifter operation.

Example –

PRE
cpsr = nzcvqift_USER
r0 = iv ; register to be compared
r9 = 4 ; register to be compared
CMP r0, r9

POST
cpsr = nzcvqift_USER output generated subsequently comparison

5. Motility Instructions –
Move is the simplest ARM teaching. It copies North into a destination register Rd, where N is a register or firsthand value. This instruction is useful for setting initial values and transferring data between registers.

Syntax – <pedagogy>{<cond>}{Due south} Rd, N

MOV	Movement a 32-scrap value into a register	Rd = N
MVN	motion the Not of the 32-bit value into a register	Rd = ~N

Case –
PRE
r5 = five ; annals value
r7 = 8 ; register value
MOV r7, r5 ;let r7 = r5

Postal service
r5 = v ; data in the register later on moving the r5 information into r7
r7 = 5 ; output after move operation

Barrel Shifter –
It is a device to shift a discussion with variable amount. It is ane of the logic devices used to pre-procedure one of the operand/register before operating on to the ALU operations. And it is i of the best features of ARM.

Barrel Shifter

Mnemonics	Description	Shift	Consequence	Shift amount
LSL	logical shift left	xLSLy	x<<y	#0-31 or Rs
LSR	logical shift right	xLSRy	(unsigned) x>>y	#i-32 or Rs
ASR	arithmetic right shift	xASRy	(signed) 10>>y	#ane-32 or Rs
ROR	rotate right	xRORy	((unsigned) 10>>y) \| (10<<(32 – y)	#1-31 or Rs
RRX	rotate right extended	xRRX	(c flag << 31) \| ((unsigned) x>>ane)	none

x represents the register existence shifted and y represent the shift amount

N shift operations	Syntax
Immediate	#immediate
Annals	Rm
Logical shift left by immediate	Rm, LSL #shift_imm
Logical shift left past annals	Rm, LSL Rs
Logical shift right by immediate	Rm, LSR #shift_imm
Logical shift right past register	Rm, LSR Rs
Arithmetic shift right past immediate	Rm, ASR #shift_imm
Arithmetic shift right by annals	Rm, ASR Rs
Rotate right by immediate	Rm, ROR #shift_imm
Rotate correct past annals	Rm, ROR Rs
rotate right with extend	Rm, RRX